1. Field of the Invention
The present invention relates to a semiconductor memory device of a large storage capacity. More particularly, it relates to a semiconductor memory device including a structure of redundant memory cell arrays which is adaptable to a data compression test for concurrently reading out data in cells of a plurality of segments.
2. Description of the Related Art
A storage capacity of a semiconductor memory device, such as a dynamic RAM (DRAM) or static RAM (SRAM), goes on increasing. According to the increase, a redundant cell array is provided in addition to a normal memory cell array to maintain a high belief of a defective cell, bit or word. If a defective bit is detected on the normal cell array, the bit is replaced to a normal bit of the redundant cell array.
On the other hand, according to the increase of the storage capacity of the memory device, a normal memory array is divided into a plurality of segments to save the consumption power. A plurality of memory cells arranged as a matrix, a plurality of bit lines linked to these memory cells and sense amplifiers for detecting potentials of each bit lines are provided in each segment. The outputs from the plurality of sense amplifiers are connected to common data bus lines through column gates. The data bus line is connected to a sense buffer for reading the common data bus or a write amplifier for writing the data bus lines in the segment. The output from the segment is connected to an I/O circuit through main data bus lines commonly used in the plurality of segments.
FIG. 1 shows a structure of a redundant cell array of the conventional semiconductor memory device. In FIG. 1, an example of a DRAM in which a memory cell MC is formed of one transistor and one capacitor is shown. In this example, four segments SGM0 to SGM3 are provided in a normal cell array 20. Each segment includes memory cells MC disposed at crossings between a word line WL and bit line pair BL and /BL, sense amplifiers SA for detecting potential differences between bit lines pair BL and /BL, as illustrated in a segment SGM0 of FIG. 1. In the example of FIG. 1, a segment SGM0 includes four columns each of which bit line pair are connected to data bus lines DB and /DB commonly used in the segment through column gates 42. The data bus lines DB and /DB are connected to a sense buffer and write amplifier 44 commonly used in the segment.
Then, the outputs from the sense buffers 44 in each of the segments SGM0 to SGM3 are connected to a main data bus line MDB commonly used in the plurality of segments. The main data bus line MDB is connected to an I/O circuit, not shown in FIG. 1.
The outputs from the plurality of sense amplifiers SA in each of the segments are connected to a sense buffer 44 through column gates 42. This column gate 42 is selected by column selection signals CL1 to CL3 generated by a column decoder 40. In the example of FIG. 1, column selection signals CL0 to CL3 are commonly supplied to the plurality of segments.
A redundant cell array 30 is provided in the example of FIG. 1. Redundant cell array 30 having the same capacity as that of each segment includes four bit line pairs, sense amplifiers, column gates, and data bus line pair RDB and /RDB for common redundancy, and further includes a commonly used sense buffer and write amplifier 32 for the redundant cell array 30. The output from sense buffer and write amplifier 32 is connected to the common main data bus line MDB.
On the other hand, a segment decoder 50 decodes column addresses Y2 and Y3, generates segment selection signals SGS0 to SGS3 for selecting one segment in normal cell array 20 and supplies the generated signals to each sense buffers 44. The output from sense buffers 44 in one segment selected by segment selection signals SGS0 to SGS3 is output to main data bus line pair MDB. In the drawing, only one line is shown for the main data bus line pair MDB.
In the example of FIG. 1, redundant cell array 30 is replaced to one segment including a defective memory cell or bit in normal cell array 20. Therefore, a redundant address ROM in a redundancy detector 34 stores column addresses Y2 and Y3 for selecting the segment in which the defective memory cell or bit exists. Redundancy detector 34 compares the supplied column addresses Y2 and Y3 with addresses in the redundancy ROM, outputs a redundant selection signal RSGS for selecting redundant cell array 30, and together, deactivates segment decoder 50 so as to inhibit to output segment selection signals SGS0 to SGS3 when both addresses are coincided. As a result, data transmitted from redundancy cell array 30 is output to main data bus MDB instead of one segment in normal cell array 20.
Hereupon, there is a need for testing normal activation of a memory. In the test, data of 0 or 1 is written to a memory cell, the data in the memory cell is read out, and it is checked whether or not the read data is coincided with the written data. However, according to the increase of a storage capacity of a memory, if the above-described test is executed to all of memory cells in order, huge test time is required, and therefore, it is not applicable for practical use.
Then, a compression test is proposed in general. In the compression test, data of 0 or 1 is concurrently written to a plurality of memory cells, and data of the plurality of memory cells are concurrently read out after that, zero is output if all of the read data are coincided with zero, 1 is output if all of the read data are coincided with 1, and an output becomes high impedance and nothing is output when at least one of all the read data is different. This enables the concurrent test for a plurality of memory cells, and therefore, makes time required for the test reduce shortly.
In the above-described compression test, as shown in FIG. 1, memory cells in each segment are concurrently selected, the outputs from sense buffers 44 in each segment are supplied to a test circuit 52 through commonly-used main data bus line pair MDB. In other word, in the compression test, a word line WL is selected and the data are concurrently written to memory cells corresponding to each segment by a column selection signal transmitted from column decoder 40 in FIG. 1. When concurrently reading out the data from the plurality of segments, main data bus line pair MDB are pre-charged to H level, sense buffers 44 in each segment are concurrently activated, for example, one of the main data bus line pair MDB is driven to L level according to the read data. Therefore, when all of the read data are the same, one of main data bus line pair MDB corresponding to the data is driven to L level, and both of the main data bus line pair MDB are also driven to L level when at least one of the read data is different. Accordingly, this enables the detection of the conditions of the read data as all H level, all L level or incoincidence by employing the main data bus line pair MDB.
However, in the above-described compression test, it is impossible to detect in which segment the defect memory cell or bit exists. Therefore, in the structure in which redundancy cell array 30 is replaced for each segment of FIG. 1, the segment to be replaced to redundancy cell array 30 cannot be detected according to the above-described compression test. Therefore, the above-described compression test is employed only in a test after replacing the segment to the redundancy cell array, exclusively, i.e., writing the data to a redundant ROM in a redundancy detector 34.